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Layout techniques for MOSFETS / Salvador Pinillos Gimenez.

Por: Tipo de material: TextoTextoSeries Synthesis lectures on emerging engineering technologies ; # 7.Editor: San Rafael, California : Morgan & Claypool Publishers, 2016Fecha de copyright: ©2016Descripción: xi, 69 páginas : ilustraciones, diagramas, tablas ; 24 cmTipo de contenido:
  • texto
Tipo de medio:
  • sin mediación
Tipo de soporte:
  • volumen
ISBN:
  • 9781627054829
  • 1627054820
  • 9781627054881
  • 162705488X
Tema(s): Clasificación LoC:
  • TK 7871.95 G55.2016
Contenidos:
1. Introduction -- 2. The origin of the innovative layout techniques for MOSFETs -- 2.1 Observing and combining different new effects in MOSFETs -- 3. Diamond MOSFET (hexagonal gate geometry) -- 4. Octo layout style (octagonal gate shape) for MOSFET -- 5. Ellipsoidal layout style for MOSFET -- 6. Fish layout style ("<" gate shape) for MOSFET -- 7. Annular circular gate layout style for MOSFET -- 8. Wave layout style ("S" gate shape) for MOSFET -- 9. Conclusions and comments -- References -- About the author.
Resumen: This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
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Libros Biblioteca Francisco Xavier Clavigero Acervo Acervo General TK 7871.95 G55.2016 (Navegar estantería(Abre debajo)) ej. 1 Disponible UIA167416

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1. Introduction -- 2. The origin of the innovative layout techniques for MOSFETs -- 2.1 Observing and combining different new effects in MOSFETs -- 3. Diamond MOSFET (hexagonal gate geometry) -- 4. Octo layout style (octagonal gate shape) for MOSFET -- 5. Ellipsoidal layout style for MOSFET -- 6. Fish layout style ("<" gate shape) for MOSFET -- 7. Annular circular gate layout style for MOSFET -- 8. Wave layout style ("S" gate shape) for MOSFET -- 9. Conclusions and comments -- References -- About the author.

This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.