TY  - BOOK
AU  - Yu,Shimeng
TI  - Resistive random access memory (RRAM): from devices to array architectures 
T2  - Synthesis lectures on emerging engineering technologies
SN  - 1627059296
AV  - TK 7895.M4 Y87.2016
PY  - 2016///
CY  - San Rafael, California
PB  - Morgan & Claypool Publishers
KW  - Nonvolatile random-access memory
KW  - Memoria de acceso aleatorio no volátil
N1  - Incluye bibliografía (páginas 57-69); 1. Introduction to RRAM technology -- 1.1 Overview of emerging memory technologies -- 1.2 RRAM basics -- 1.3 Recent research and development of RRAM technology --; 2. Device fabrication and performances -- 2.1 Device fabrication: forming-free and scalability -- 2.2 Device performances -- 2.3 Device reliability --; 3. RRAM characterization and modeling -- 3.1 Overview of RRAM physical mechanism -- 3.2 Materials and electrical characterization -- 3.3 Numerical modeling using kinetic Monte-Carlo method -- 3.4 Compact modeling for spice simulation --; 4. RRAM array architecture -- 4.1 1T1R array -- 4.2 Cross-point array -- 4.3 Selector device -- 4.4 Peripheral circuits design -- 4.5 3D integration --; 5. Outlook for RRAM's applications -- Bibliography -- Author biography
N2  - RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM's potential novel applications beyond the NVM applications
ER  -