000			03336nam a2200433 i 4500
001			000693278
003			OCoLC
005			20240105153004.0
008			170516t20162016caua rb 000 0 eng d
020			_a9781627054829
020			_a1627054820
020			_a9781627054881
020			_a162705488X
035			_a419520
040			_aCaBNVSL _bspa _erda _cJ2I _dUIASF
050		4	_aTK 7871.95 _bG55.2016
100	1		_aGimenez, Salvador Pinillos _d1962- _eautor
245	1	0	_aLayout techniques for MOSFETS / _cSalvador Pinillos Gimenez.
264		1	_aSan Rafael, California : _bMorgan & Claypool Publishers, _c2016
264		4	_c©2016
300			_axi, 69 páginas : _bilustraciones, diagramas, tablas ; _c24 cm.
336			_atexto _btxt _2rdacontent
337			_asin mediación _bn _2rdamedia
338			_avolumen _bnc _2rdacarrier
490	1		_aSynthesis lectures on emerging engineering technologies _v7
504			_aIncluye referencias bibliográficas (páginas 61-68).
505	0		_a1. Introduction -- 2. The origin of the innovative layout techniques for MOSFETs -- 2.1 Observing and combining different new effects in MOSFETs -- 3. Diamond MOSFET (hexagonal gate geometry) -- 4. Octo layout style (octagonal gate shape) for MOSFET -- 5. Ellipsoidal layout style for MOSFET -- 6. Fish layout style ("<" gate shape) for MOSFET -- 7. Annular circular gate layout style for MOSFET -- 8. Wave layout style ("S" gate shape) for MOSFET -- 9. Conclusions and comments -- References -- About the author.
520	3		_aThis book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
650		0	_aMetal oxide semiconductor field-effect transistors.
650		4	_aTransistores de efecto de campo
650		0	_aIntegrated circuit layout.
650		4	_aDisposición de circuitos integrados
830		0	_aSynthesis lectures on emerging engineering technologies _v# 7.
905			_a01
942		1	_cNEWBFXC1
999			_c648987 _d648987
980			_851 _gRonald RUIZ