Incluye referencias bibliográficas (páginas 63-69).

1. Review of research on scaled device architectures and importance of lower substrate temperature operation of n-MOSFETs -- 1.1 Introduction and scope of this e-book -- 1.2 Basic overview and operational salient features of n-channel MOSFET device transport -- 1.3 Review of challenges and bottlenecks experienced over sustained MOSFET device scaling -- 1.4 Device parameters critical for performance enhancement for generalized scaling and at the end of Moore's Law -- 1.5 Role of substrate temperature modeling and control --

2. Step-by-step computation of threshold voltage as a function of substrate temperatures -- 2.1 Essential modeling equations for computation of threshold voltage of N-channel MOSFET as a function of substrate/lattice temperature --

3.Simulation outcomes for profile of threshold voltage as a function of substrate temperature based on key device-centric parameters -- 3.1 Simulation outcomes of various n-MOSFET device parameters including threshold voltage as a function of temperature -- 3.2 Simulation outcome of intrinsic carrier concentration (ni ) as a function of substrate or lattice temperature -- 3.3 Simulation outcome of incomplete ionization of Dopants relevant for lower substrate temperature operation -- 3.4 Simulation outcome of Fermi energy level EF (eV) as a function of temperature -- 3.5 Temperature dependence of flat band voltage [phi]ms (V) -- 3.6 P-type substrate n-channel MOSFET bulk potential dependence on substrate/lattice temperature -- 3.7 Dependence of threshold voltage VT of n-channel MOSFET on substrate temperature for 1 micro channel length MOSFET -- 3.7.1 Modeling impact of incomplete ionization on threshold voltage at the freeze-out temperature region: a closer look -- 3.8 Threshold voltage dependence on substrate temperature for different substrate doping conditions for an n-channel MOSFET -- 3.9 Threshold voltage dependence on substrate temperature for different oxide thickness for an n-channel MOSFET -- 3.10 Threshold voltage dependence on substrate temperature for negative substrate bias for an n-channel MOSFET -- 3.11 Threshold voltage dependence on substrate temperature for positive substrate bias for an n-channel MOSFET --

4. Scaling projection of long channel threshold voltage variability with substrate temperatures to scaled node -- 4.1 Modeling and simulation results for a long channel MOSFET as channel length is scaled further --

5. Advantage of lower substrate temperature MOSFET operation to minimize short channel effects and enhance reliability -- 5.1 Low substrate temperature MOSFET modeling benefits in consideration of short channel effects --

6. A prospective outlook on implementation methodology of regulating substrate temperatures on silicon die -- 6.1 A short outlook on implementation of low substrate temperature MOSFET modeling and control --

7. Summary of research results -- 7.1 Summary of research outcomes --

8. Conclusion -- References -- Authors' biographies.

In order to sustain Moore's Law-based device scaling, principal attention has focused on toward device architectural innovations for improved device performance as per ITRS projections for technology nodes up to 10 nm. Efficient integration of lower substrate temperatures (<300K) to these innovatively configured device structures can enable the industry professionals to keep up with Moore's Law-based scaling curve conforming with ITRS projection of device performance outcome values. In this prospective review E-book, the authors have systematically reviewed the research results based on scaled device architectures, identified key bottlenecks to sustained scaling-based performance, and through original device simulation outcomes of conventional long channel MOSFET extracted the variation profile of threshold voltage as a function of substrate temperature which will be instrumental in reducing subthreshold leakage current in the temperature range 100K-300K. An exploitation methodology to regulate the die temperature to enable the efficient performance of a high-density VLSI circuit is also documented in order to make the lower substrate temperature operation of VLSI circuits and systems on chip process compatible.